Customers adopting Design Compiler NXT report significant reduction in runtimes together with improvements in power, performance and area (PPA) New advanced optimizations, such as concurrent clock and ...

PARIS — EDA and IP vendor Synopsys Inc. (Mountain View, Calif.) said it has extended its topographical technology in Design Compiler 2010 to produce physical guidance to its place-and-route solution, ...

Broad deployment of Design Compiler Graphical for Samsung Mobile SoCs Reduced routing congestion leads to 10 percent smaller area for highly congested blocks Minimal use of Low-Vt cells reduces ...

AMD deploys Synopsys' Fusion Compiler RTL-to-GDSII product for the development of its next-generation processor products Unique, single-data-model architecture and unified, full-flow optimization ...

Synopsys' Design Compiler 2010 accounts for the challenges of modern physical IC design, offering floor plan exploration from within the synthesis environment. It also delivers physical guidance to IC ...

Synopsys has announced that its AI-driven digital design and analog design flows have achieved certification on Samsung Foundry's SF2 process with multiple test chip tape-outs. The reference flows, ...

How a next‑gen SRAM compiler IP for TSMC N5A and N3A helps design teams with measurable gains in PPA, reliability, and system ...

SANTA ROSA, Calif--(BUSINESS WIRE)--Keysight Technologies, Inc. (NYSE: KEYS), a leading technology company that delivers advanced design and validation solutions to help accelerate innovation to ...

The Arm and Synopsys partnership is now extended to the new Arm data center CPU, including EDA, IP, and hardware-assisted verification solutions ...

SANTA CLARA, Calif. & MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--SiFive and Synopsys, Inc. (Nasdaq: SNPS) today announced their new collaboration to accelerate the design and verification of SiFive ...