Nature

Low-Density Parity-Check Decoder Architectures and Algorithms

Low-Density Parity-Check (LDPC) decoder designs have undergone significant evolution, driven by the need for high-throughput, low-complexity and energy-efficient ...
EDN

Low power LDPC decoder created using high level synthesis

HLS methodology allows the hardware design to be completed at a higher level of abstraction such as C/C++ algorithmic description. This provides significant time and cost savings, and paves the way ...
TechRepublic

Low-Complexity Encoding of LDPC Codes: A New Algorithm and its Performance

A new technique for efficient encoding of LDPC codes based on the known concept of Approximate Lower Triangulation (ALT) is introduced. The greedy permutation algorithm is presented to transform ...
Design-Reuse

CCSDS AR4JA LDPC Encoder and Decoder FEC IP Core Available For Licensing and Implementation from Global IP Core

January 9, 2023 - Global IP Core Sales - The new CCSDS AR4JA LDPC Encoder and Decoder FEC IP Core is a configurable design that allows runtime configuration for decoding different code rates (i.e., ...
Design-Reuse

DVB-T2 Demodulator + Decoder LDPC/ BCH IP Core Available For Immediate Implementation From Global IP Core

March 7, 2023 - Global IP Core Sales - The new DVB-T2 demodulator is designed to be used together with an RF tuner, and an analog to digital converter. The system has an internal state machine to ...
EDN

LSI brings LDPC technology to disk read-channels

LSI officially launched a new era in disk read-channel technology this week with the RC9500: a new generation mixed-signal read channel intellectual property (IP) core cluster. The block, intended for ...